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Fix RTL structure, module reference, and add Pocket-LLM compiler
- #8
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Sep 6, 2026
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Fix RTL structure, module reference, and add Pocket-LLM compiler
#8
mathcode220-math
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mathcode220-math/open-cognitive-core:main
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jules-1156097177584587582-97777593
mathcode220-math/open-cognitive-core:jules-1156097177584587582-97777593
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Fix RTL module imports and directory name, add Pocket-LLM compiler
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Fix Verilator DECLFILENAME lint warning in systolic_array_param.sv
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Add --main flag to Verilator flags in sim/Makefile
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Fix Verilator lint warnings in axi4_lite_core_ctrl and testbench
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