Fix RTL structure, module reference, and add Pocket-LLM compiler - #8
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- Move liquid_processing_element.sv into clean rtl/math_core directory - Update open_cognitive_top.sv to instantiate hdc_ngram_encoder_v3 - Implement occp_compiler.py for weight tiling, INT8 quantization and binary export Co-authored-by: mathcode220-math <245710882+mathcode220-math@users.noreply.github.com>
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- Add verilator lint_off DECLFILENAME pragma in systolic_array_param.sv to handle pe module declaration without errors Co-authored-by: mathcode220-math <245710882+mathcode220-math@users.noreply.github.com>
- Add --main flag to VERILATOR_FLAGS in sim/Makefile so Verilator generates C++ main wrapper when building testbench executables Co-authored-by: mathcode220-math <245710882+mathcode220-math@users.noreply.github.com>
- Remove unused byte_write_en variable in axi4_lite_core_ctrl.sv - Add UNUSEDSIGNAL lint pragmas for unused signals - Use non-blocking assignment for clock generation in tb_axi4_lite_core_ctrl.sv Co-authored-by: mathcode220-math <245710882+mathcode220-math@users.noreply.github.com>
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Fixed RTL directory structure typo (removed trailing space in folder name), corrected SystemVerilog module reference in top module, and added the Pocket-LLM hardware compiler script (
occp_compiler.py) following documentation specifications. Verified with tests.PR created automatically by Jules for task 1156097177584587582 started by @mathcode220-math