Update from task 416aaebf-5441-47ed-920b-d4bfaf3f2540

.gitignore

@@ -1,27 +1,74 @@
 ```
-# Compiled and build artifacts
-*.o
-*.obj
-*.out
-sw/occp_bridge_test
-
-# Dependencies
-node_modules/
-venv/
-.venv/
-__pycache__/
-
 # Logs and temp files
 *.log
 *.tmp
 *.swp
 
-# Editors
-.vscode/
-.idea/
-
 # Environment
 .env
 .env.local
 *.env.*
+
+# Editors
+.vscode/
+.idea/
+
+# Dependencies
+node_modules/
+venv/
+.venv/
+__pycache__/
+.mypy_cache/
+.pytest_cache/
+dist/
+build/
+target/
+.gradle/
+
+# OS generated files
+.DS_Store
+Thumbs.db
+
+# Python specific
+*.pyc
+*.pyo
+*.pyd
+*.egg-info/
+.coverage
+coverage/
+htmlcov/
+
+# Compiled files
+*.class
+*.o
+*.obj
+*.exe
+*.dll
+*.so
+*.a
+*.out
+
+# Archives
+*.zip
+*.gz
+*.tar
+*.tgz
+*.bz2
+*.xz
+*.7z
+*.rar
+*.zst
+*.lz4
+*.lzh
+*.cab
+*.arj
+*.rpm
+*.deb
+*.Z
+*.lz
+*.lzo
+*.tar.gz
+*.tar.bz2
+*.tar.xz
+*.tar.zst
 ```

Pocket-LLM/compiler/README.md

@@ -188,28 +188,32 @@ Each tile is stored in row-major order:
 
 ## Integration with Hardware Bridge
 
+The complete AI-to-Silicon pipeline connects the Pocket-LLM compiler with the OCCP hardware:
+
 ```python
-# Python: Generate compiled binary
+# Python: Generate compiled binary from model weights
 compiler = OCCPCompiler(enable_quantization=True)
 compiler.compile_model(layer_name="attention.q_proj", rows=64, cols=64)
 
-# Output: compiled_model.bin
+# Output: compiled_model.bin (Row-Major format)
 ```
 
 ```c
-// C: Load and execute binary
+// C: Load and execute binary on silicon
 FILE *f = fopen("compiled_model.bin", "rb");
 float tile[4];
 
 while (fread(tile, sizeof(float), 4, f) == 4) {
     float result[4];
     occp_dispatch_matrix_multiply(tile, identity_matrix, result);
-    // Process result...
+    // Stream results to SRAM Skew Buffer -> Systolic Array
 }
 
 fclose(f);
 ```
 
+For detailed C-Driver API reference, see: [OCCP Software Bridge Documentation](https://github.com/mathcode220-math/-Pocket-LLM-/tree/main/sw)
+
 ## Future Enhancements
 
 - [ ] Real ONNX/TFLite model parsing

doc/ARCHITECTURE.md

@@ -4,6 +4,45 @@
 
 The Open Cognitive Core Project (OCCP) is a hardware accelerator for Hyperdimensional Computing (HDC) and lightweight neural network operations, designed for FPGA implementation.
 
+## Data Pipeline & Hardware Handshake
+
+The compilation artifacts from **Pocket-LLM** directly feed into the core hardware registers. Below is the precise interaction map:
+
+1. **Pocket-LLM Compiler** processes tensors ➡️ Outputs `compiled_model.bin` (Row-Major format).
+2. **Open-Cognitive-Core (C-Driver)** loads the binary ➡️ Streams data directly into the **SRAM Skew Buffers**.
+
+```
++-------------------+     compiled_model.bin     +---------------------------+
+|   Pocket-LLM      | -------------------------> |  Open-Cognitive-Core      |
+|   Compiler        |  (Row-Major Binary Format) |  (C-Driver / Silicon)     |
+|                   |                            |                           |
+| - Loads ONNX/     |                            | - occp_bridge.c           |
+|   PyTorch models  |                            | - Memory-mapped I/O       |
+| - Tiles matrices  |                            | - AXI4-Lite interface     |
+| - Quantizes to    |                            |                           |
+|   INT8/Float32    |                            | +-----------------------+ |
+| - Exports binary  |                            | | SRAM Skew Buffer      | |
++-------------------+                            | | (Cycle delays for     | |
+                                                 | |  systolic timing)     | |
+                                                 | +----------+------------+ |
+                                                 |            |              |
+                                                 |            v              |
+                                                 | +----------+------------+ |
+                                                 | | Systolic Array        | |
+                                                 | | (Matrix multiply      | |
+                                                 | |  engine)              | |
+                                                 | +----------+------------+ |
+                                                 |            |              |
+                                                 |            v              |
+                                                 | +----------+------------+ |
+                                                 | | ReLU / Softmax        | |
+                                                 | | (Activation units)    | |
+                                                 | +-----------------------+ |
+                                                 +---------------------------+
+```
+
+For the low-level silicon implementation and C-Driver specifications, please refer to the main repository: [Pocket-LLM](https://github.com/mathcode220-math/-Pocket-LLM-).
+
 ## System Architecture
 
 ```

sw/README.md

@@ -139,15 +139,39 @@ Check if physical hardware is detected.
 | `0x40000020` | SRAM B | Matrix input buffer B |
 | `0x40000030` | SRAM Result | Output buffer |
 
-## Integration with Pocket-LLM
+## Integration with Pocket-LLM Compiler
 
-The typical workflow:
+The typical workflow for the complete AI-to-Silicon pipeline:
 
 1. **Pocket-LLM Compiler** reads model weights and tiles them into 2x2 matrices
-2. Compiled weights are saved as `compiled_model.bin`
+2. Compiled weights are saved as `compiled_model.bin` in Row-Major format
 3. This C driver reads the binary file and calls `occp_dispatch_matrix_multiply()` for each tile
 4. Results are streamed back to Pocket-LLM for text generation
 
+```
++------------------+     compiled_model.bin     +------------------+
+|  Pocket-LLM      | -------------------------> |  OCCP C-Driver   |
+|  Compiler        |  (Row-Major Binary Format) |  (occp_bridge.c) |
+|                  |                            |                  |
+| - Model weights  |                            | - Loads binary   |
+| - Tiling engine  |                            | - Streams to     |
+| - Quantization   |                            |   SRAM buffers   |
++------------------+                            +--------+---------+
+                                                         |
+                                                         v
+                                                +--------+---------+
+                                                |  OCCP Silicon    |
+                                                |  Co-Processor    |
+                                                |                  |
+                                                | - SRAM Skew      |
+                                                |   Buffer         |
+                                                | - Systolic Array |
+                                                | - ReLU/Softmax   |
+                                                +------------------+
+```
+
+For detailed compiler specifications and API reference, see: [Pocket-LLM Compiler Documentation](https://github.com/mathcode220-math/-Pocket-LLM-/tree/main/compiler)
+
 ## Troubleshooting
 
 ### "Hardware timeout! Chip not responding."