Improve Documentation of CPLD/FPGA Programming

[awalsemann]

• The text section for Exercise 3 (ToT Counter) should also contain a diagram showing the digital logic implemented in the CPLD from the AFE chapter, as well as a short text explaining its function. Otherwise, it is unclear, for example, what the HIT output signal's function is.
• The JTAG connection between the RPi's software JTAG master and the CPLD is not documented. Therefore, it is unclear which of the RPi's GPIOs are to be used.