UVM Simple Example

A simple SystemVerilog UVM memory testbench supporting AMD Xilinx Vivado Simulator (XSIM) and the UVM-enabled iverilog-uvm fork.

Run a simulation

XSIM is the default simulator.

make run

Choose a simulator explicitly with either its USE_* variable or a manual invoke target.

# XSIM
make run USE_XSIM=1
make xsim_run

# iverilog-uvm
make run USE_IVERILOG=1
make iverilog_run

TEST_NAME defaults to mem_test and can be overridden at invocation time.

make iverilog_run TEST_NAME=mem_test

VCD dump

VCD dumping is disabled by default. Add VCD=1 to pass the +VCD plusarg to the testbench and write dump.vcd in the project root.

make xsim_run VCD=1
make iverilog_run VCD=1

XSIM setup

Either source the Vivado environment before running, or adjust the path in xsim.mk.

source /tools/Xilinx/Vivado/<version>/settings64.sh
make xsim_run

Use the GUI target when needed.

make xsim_gui

iverilog-uvm setup

Install the iverilog-uvm fork and ensure its iverilog executable is on your PATH. This project does not support the upstream Icarus Verilog distribution because it does not include the required UVM support. The compile command in iverilog.mk uses the SystemVerilog-2023 language generation option.

make iverilog_run

Clean generated files

Clean artifacts generated by both simulators.

make clean