PR #493 changed how register accesses are proven (removed MEMW_R, added REGISTER_RELOAD, moved the access logic into the CPU chip). These changes were made directly in the prover and are not reflected in specs_vm/spec/.
Before this can be considered final we need to investigate:
- Is the new model (register accesses on the CPU chip +
REGISTER_RELOAD for gaps > 65534) the one we want to commit to long-term, or a temporary perf hack?
- If it stays, the spec needs to be updated: drop
MEMW_R, add REGISTER_RELOAD, and document the new CPU columns and Memory-bus interactions.
- If not, decide what the spec-compliant version looks like and whether the perf gain (-31% prove time) justifies the divergence in the meantime
PR #493 changed how register accesses are proven (removed
MEMW_R, addedREGISTER_RELOAD, moved the access logic into the CPU chip). These changes were made directly in the prover and are not reflected inspecs_vm/spec/.Before this can be considered final we need to investigate:
REGISTER_RELOADfor gaps > 65534) the one we want to commit to long-term, or a temporary perf hack?MEMW_R, addREGISTER_RELOAD, and document the new CPU columns and Memory-bus interactions.